The present invention relates to an evaluation method and a fabrication method of a semiconductor device, and an apparatus and a program for evaluating the semiconductor device, and more particularly relates to a method for evaluating an insulating film in a short time and with high accuracy.
With the recent advancement of semiconductor devices to a higher degree, a demand for flash memories has been growing. In a flash memory, electrons are exchanged through an insulating film (i.e., a tunnel oxide film), and thus the characteristics of the insulating film have a large effect on device performance.
FIG. 1A is a cross-sectional view illustrating a typical cell structure of a flash memory. In the structure of FIG. 1A, a floating gate 12 is formed over a silicon substrate 10 with a tunnel oxide film interposed therebetween. A control gate 14 is formed over the floating gate 12 with a capacitance insulating film 13 interposed therebetween. Electrons are stored in the floating gate and thereby information is recorded. In the flash memory, after the electrons have been stored in the floating gate, the electrons gradually go off from the floating gate with time, resulting in change in threshold voltage. This phenomenon is called “retention characteristic”.
FIG. 1B is a graph illustrating typical behaviors for the retention characteristic. In FIG. 1B, the abscissa indicates the time at log scales, while the ordinate indicates the threshold voltage. The curve a of FIG. 1B representing the most typical behavior for the retention characteristic shows that the electrons go off from the floating gate with time and that the threshold voltage gradually decreases. This behavior has been observed with respect to almost all bits. In contrast, the curve b shows that the electrons abruptly go off from the floating gate, resulting in a sharp drop of the threshold voltage. That is to say, the retention characteristic is markedly degraded. Such a phenomenon has been observed with respect to very few bits and is called “retention failure”. As for the occurrence of a retention failure, various possible causes nave been considered. One of them is an anomalous leakage current (ALC) through a tunnel oxide film, which will be herein referred to as a “μB-SILC (micro B-mode stress induced leakage current)”. The retention failure due to a μB-SILC will be herein referred to as “retention degradation”.
The evaluation method of FIG. 2 is one of known methods for determining the retention degradation, which have been previously used.
FIG. 2 is a flowchart illustrating a method for evaluating the occurrence of retention degradation in a tunnel oxide film (indicated by the curve b of FIG. 1).
First, in Step (a), a program/erase operation (which will be herein referred to as a “P/E operation”) is repeatedly performed a predetermined number of times (e.g., 10,000 times in this case) for each of the all memory cells (e.g., 16M bits), thereby applying stress to the insulating film. After the P/E operations have been completed, the memory cells are all programmed in Step (b).
Then, in Step (c), threshold voltages (Vth values) of all the memory cells at the time when the programming has been completed are recorded. Thereafter, in Step (d), all the memory cells are left to stand for a predetermined period of time (e.g., 100 hours in this case). After the predetermined time has passed, the Vth values for all the memory cells are measured again in Step (e). In Step (f), the Vth values that are obtained in Step (e) are compared to those recorded in Step (c), and then calculated are variations of the Vth values during the time period in which the cells have been left to stand. These process steps are performed at various time settings for the cells being left to stand, as necessary, so as to ascertain the number of μB-SILC occurrences in the samples and the time which it takes before a μB-SILC occurs in each sample.
However, there have been several problems with the above described method. One of them is that the stress application in Step (a) requires an enormous amount of time. Also, a huge amount of memory cell information has to be recorded in Steps (c) and (e) and made comparison in Step (f). In order to increase the accuracy in determination of the retention degradation, the memory cells have to be left to stand for several hundred to several thousand hours in Step (d). In addition, as the insulating film is improved so as to have higher quality, the retention failure occurs less readily. Accordingly, an increased number of samples need to be evaluated, and thus a longer time is required for the evaluation.
It is therefore an object of the present invention to provide a method for determining the retention degradation of a semiconductor device, such as a flash memory, in which a less number of measurements are performed in a short time and with high accuracy.